1. Field of the Invention
The present invention relates to a semiconductor device comprising a memory cell array having a hierarchical bit line structure in which there are redundant memory cells for replacing normal memory cells that are defective, and relates to a control method thereof and a data processing system comprising the semiconductor device.
2. Description of Related Art
In semiconductor memory devices of recent years such as a DRAM, an increase in capacity and a reduction in size have been achieved, which causes the number of memory cells on a bit line to increase. In order to deal with this performance problem, hierarchical bit lines including global bit lines and local bit lines tend to be employed. In general, the hierarchical bit lines are provided with hierarchical switches controlling connections between the global bit lines and the local bit lines. In this kind of the hierarchical bit lines, when sense amplifiers are connected to one ends of the global bit lines, it is necessary to previously precharge the global bit lines and the local bit lines to a common potential prior to accessing memory cells. In this case, if a precharge circuit is provided for each of a large number of local bit lines for one global bit line, a circuit scale thereof increases. Therefore, by appropriately controlling the hierarchical switches, a precharge circuit for the global bit line is desired to be commonly used in a precharge operation of the local bit lines. For example, Patent Reference 1 discloses a control method of the hierarchical switches that enable precharging the local bit lines using the precharge circuit for the global bit line in a memory cell array having the hierarchical bit lines.    [Patent Reference 1] Japanese Patent Application Laid-open No. 2007-287209 (U.S. Pat. No. 7,460,388)
A semiconductor device of large capacity such as a DRAM is generally provided with redundant memory cells for replacing normal memory cells for the purpose of repairing defective memory cells. If a redundant region including the normal memory cells and the redundant memory cells is formed in the above memory cell array having the hierarchical bit lines, there is provided a redundancy determination circuit for determining whether or not an address of an access target is a defective address when accessing a memory cell. Therefore, an operation procedure is necessary in which a hierarchical switch corresponding to the precharge operation of the hierarchical bit lines to be accessed is controlled after waiting for a determination result of the redundancy determination circuit when accessing a normal memory cell. Since it takes a relatively long time to obtain the determination result of the redundancy determination circuit, there is a risk that driving timing of a word line or a redundant word line may be delayed after the precharge operation of the hierarchical bit lines is completed, thereby decreasing access speed. Meanwhile, all hierarchical bit lines (a plurality of local bit lines corresponding to one global bit line) can be previously precharged in a standby state in order to shorten the time required to control the hierarchical switches. However, this control is not desired since an increase in consumption current of the semiconductor device is inevitable. Further, bringing a plurality of hierarchical switches corresponding to the plurality of local bit lines that are not to be accessed into a non-selected state is not desired in a viewpoint of the consumption current. In this manner, when the redundant region is formed in the memory cell array having the conventional hierarchical bit lines, there is a problem that it is difficult to keep a high access speed when accessing the memory cells without increasing the consumption current.